The RCA Standard Clean developed by Werner Kern and other RCA scientists in the late 60's is extremely effective in removing contamination from silicon surfaces of semiconductor wafers and is today and has been the defacto industry standard for more than a quarter of a century.
The rapid progress in the semiconductor industry, due in large part to the effectiveness of RCA clean (i.e., SC1/SC2), is described in detail in Werner Kern's 1993 book “Handbook of Semiconductor Wafer Cleaning” (680 pages). This progress is also discussed in “Microchip Fabrication: A Practical Guide to Semiconductor Processing” (Second Edition, 1990) by Peter Van Zant.
Unless the context or logic suggests otherwise, the terminology, abbreviations and/or jargon employed herein is intended to have a meaning consistent with the usage set forth in these Kern and Van Zant books as would be understood by those skilled in the semiconductor art.
The industry reduced the circuit image size (also known as the line width or feature size) from 0.35 micron (mm) to 0.25 micron about five years ago. The leading industry group SEMATECH, has set forth a detailed proposal for the 0.25 Micron Process which calls for around 360 process steps including more than 50 wet cleans. The detailed specifications (Steps 1 to 362) are set forth on pages B-3 to B-14 of the special printed SEMATECH publication, Technology Transfer No. 95042802-ENG. A large number of cleaning steps involve SC1, SC2 or other RCA clean features, most or all of which could be modified in accordance with my invention to permit effective removal of extremely small or colloidal-size silica particles with a diameter of 0.05 to 0.1 micron or less which cannot be removed with current technology.
The 360-step wafer fabrication process described above involves only four basic operations. They are (1) layering, (2) patterning, (3) doping, and (4) heat treatments. A detailed overview of the wafer-fabrication process is set forth in Chapter 5 of the 1990 Van Zant book which is incorporated herein by reference. Pages 95 to 99 describe 11 basic steps employed in the formation of an MOS metal-gate transistor structure.
Cleaning steps 175, 212, 248, 284, and 320 of the aforesaid 362-step fabrication scheme shown on pages B-3 to B-14, described as Clean Post CMP, are critically important and pose a difficult problem.
This year the advanced microchips have a circuit image size (also known as the line width or feature size) in the range of from 0.06 to 0.09 micron where particles with a minute size, such as 0.01 to 0.03 micron can be ruinous.
Prior to the invention, proposed improvements in wet cleaning and dry cleaning techniques offered no real hope of eliminating significant contamination by sub 0.1 micron silica particles. Therefore, killer defects were expected and could prevent the semiconductor industry from achieving its optimistic defect goals for high volume manufacturing. The national SEMATECH road map has set forth model defect density (and, by inference, yield) requirements by technology generation. Table 1 is a portion of such road map related to defect density goals.
TABLE 1Defect Goal TrendsDRAM equiv.16 Mb64 Mb256 Mb1 GbMin. dimension0.50 μm0.35 μm0.25 μm0.18 μmDefects/cm20.1 (87%)0.05 (90%)0.03 (90%)0.01 (95%)(% Yield)# ofdefect# ofdefect# ofdefect# ofdefectdefectssizedefectssizedefectssizedefectssizeKiller defects280.10 μm140.07 μm90.05 μm30.03 μmper 200 mmwafer*
In recent years chemical-mechanical planarization (CMP), makes it possible to employ smaller and smaller line widths. Unfortunately CMP involves colloidal polishing that tends to promote excessive contamination with particles of aluminum oxide, silica and the like.
In today's submicron integrated circuit technology, 0.05-micron-diameter particles can be major sources of circuit failure. Particles as small as 0.02 to 0.03 micron are now becoming major problems.